The present invention is directed to a computer processor. More particularly, the present invention is directed to a technique for synchronizing faults in a processor having a replay system.
The primary function of most computer processors is to execute computer instructions. Most processors execute instructions in the programmed order that they are received. However, some recent processors, such as the Pentium(copyright) II processor from Intel Corp., are xe2x80x9cout-of-orderxe2x80x9d processors. An out-of-order processor can execute instructions in any order as the data and execution units required for each instruction becomes available. Moreover, the execution of instructions can generate a wide variety of exceptions or faults. A fault handler or exception handler is typically called to handle the fault or exception. Detailed fault information should be stored to allow the fault handler to process or handle the fault. Maintaining the proper fault information can be a complex task, especially for an out of order processor. The prior art has not adequately addressed this problem, particularly where multiple program flows are active.
Therefore, there is a need for a technique to maintain the proper fault information to allow a fault handler to process the fault.
According to an embodiment, a processor is provided including a replay system to replay instructions which have not executed properly and a first event pipeline coupled to the replay system to process instructions including any replayed instructions. A second event pipeline is provided to perform additional processing on an instruction. The second event pipeline has an ability to detect one or more faults occurring therein. The processor also includes a synchronization circuit coupled between the first event pipeline and the second event pipeline to synchronize faults occurring in the second event pipeline to matching instruction entries in the first event pipeline.